The present invention relates to memory systems; more particularly, the present invention relates to transferring data across a memory repeater chip in a Rambus memory subsystem.
A Rambus Dynamic RAM (RDRAM) developed by Rambus, Inc., of Mountain View, Calif., is a type of memory that permits data transfer operations at speeds up to 1.2-1.6 gigabytes per second. RDRAM devices are typically housed in Rambus in-line memory modules (RIMMs) that are coupled to one or more Rambus channels. Typically, the expansion channels couple each RDRAM device to a memory controller. The memory controller enables other devices, such as a Central Processing Unit (CPU), to access the RDRAMs.
RDRAM based memory subsystems may include repeaters coupled to the expansion channel that monitor the expansion channel for activity and repeat the activity on one or more of the stick channels coupled thereto. FIG. 5 is a block diagram of an exemplary repeater. The repeater includes a slave Rambus Asic Cell (RAC) and two master RACs. The slave RAC is coupled to the expansion channel, while the master RACs are each coupled to a stick channel. The RACs are used to interface with the high frequency expansion or stick channels. Typically, a plurality of RDRAM devices are coupled to each of the stick channels.
The slave RAC operates various portions of its logic on one of three clocks (e.g., a slave receive clock and two slave transmit clocks). The master RACs also operate their logic using three different clocks (e.g., a master receive clock and two master transmit clocks). In the described mechanism, the receive clocks in the slave RAC and master RACs are synchronized via a phase locked-loop (PLL) in order to transfer data within the repeater at speeds up to 400 Mhz. Whenever commands and data is to be written to an RDRAM on one of the stick channels, the data must be transmitted from the expansion channel through the slave RAC and across the repeater chip to a master RAC. The slave RAC receives commands and data with the slave receive clock and uses the slave receive clock to transmit the commands and data across the chip to the particular master RAC.
A problem exists, however, in sampling the command and data signals at a master RAC at such a high speed. Considering clock jitters and phase errors, sampling the signals reliably in a master RAC with the master receive clock is often difficult because the lack of sufficient hold times. For instance, hold time violations would imply that delay must be added to the signal path. However, adding the requisite time delay to fix the hold time problem could potentially cause a setup time violation. Taking into consideration the problems stated above and the long cross chip distance for data transfer, it would be desirable to provide a mechanism for providing cross chip transfers at high speeds of communication.